1. Field of the Invention
The present invention is related to a DC/DC converter circuit and controller thereof; and in particular, to a charge pump control circuit and controller thereof.
2. Description of Related Art
Refer first to FIG. 1, which shows a circuit diagram of a conventional charge pump control circuit (also commonly known as switched capacitor converter). The illustrated charge pump control circuit comprises a full-bridge switching circuit, a first capacitor Cin, a second capacitor Cout, a voltage feedback circuit 30 and a control component 10. The full-bridge switching circuit consists of four transistor switches SW1˜SW4 controlled by the control signals Con_1, Con_2 sent from the control component 10. When the control signal Con_1 is high, the transistor switches SW1, SW2 become conducting and a first conducting path is accordingly formed, and the first capacitor Cin stores the electric power transferred from an input power source VDD through the first conducting path; whereas, when the control signal Con_2 is high, the transistor switches SW3, SW4 become conducting and a second conducting path is formed, the first capacitor Cin transfers the electric power to the second capacitor Cout through the second conducting path, such that the second capacitor Cout generates an output voltage Vout to the load (not shown).
The control component 10 comprises an oscillator 12, a clock controller 14 and a hysteresis comparator 16. The hysteresis comparator 16 compares the voltage feedback signal VFB generated by the voltage feedback circuit 30 with a reference voltage V1, and accordingly generates a detection signal DET. The clock controller 14 receives the detection signal DET and a clock signal CLK generated by the oscillator 12, and generates in a time-division fashion the control signals Con_1, Con_2 based on the level of the received clock signal CLK.
Next, refer to FIG. 2, wherein a timing diagram of the signals of the charge pump control circuit depicted in FIG. 1 is shown. At the time point t1, the voltage feedback signal VFB is lower than the reference voltage V1−, and at this moment the detection signal DET transits from low level to high level. However, the clock signal CLK is at low level, which is the time window for generating the control signal Con_1, and the control component 10 outputs a high control signal Con_1, a low control signal Con_2, and the second conducting path is open, thus the first capacitor Cin is not allowed to transfer power to the second capacitor Cout. This causes the output voltage Vout to fall consistently until the time point t2 is reached. At time point t2, the clock signal CLK is high; i.e., the time window for generating the control signal Con_2, and the control component 10 outputs a low control signal Con_1 and a high control signal Con_2, and the first capacitor Cin transfers power to the second capacitor Cout through the second conducting path, such that the output voltage Vout starts to rise again until the reference voltage V1+ (at time point T3) is reached. Whereas, during the period of time from time point t1 to time point t2, the output voltage Vout keeps falling, and the maximum difference from the reference voltage V1− can be up to ΔV. As a result, the output voltage ripple in the conventional charge pump control circuit can not be controlled within an expected range that is presented by a greater voltage ripple, and this situation also occurs in circuits with the same operating mode (i.e. circuits that has the generation time point of control signal determined by the clock signal CLK).